This invention relates to a display controller for a flat display apparatus which is suitable for such information processing apparatus as work stations using flat display panels such as liquid crystal display panels.
In currently available display controllers intended for fine display of information, as employed in work stations and the like, it is a general convention to speed up the multiple color and variable color functions based on a lookup table, as described in Japanese Patent Publication No. 54-37943. The following explains the above-mentioned prior art with reference to FIGS. 1 and 2.
FIG. 1 is a block diagram of the conventional display controller. In the figure, indicated by 1 is an oscillator which generates a base clock signal (dot clock signal) 2, with each clock pulse corresponding to a pixel (dot) of the display, and 3 is a timing signal generation circuit which produces various timing signals from the dot clock signal 2. A character clock signal for of a 8-dot interval is produced by the timing signal generation circuit 3, and a display address generation circuit 5 repeatedly generates display addresses for one frame in accordance with the character clock signal 4. A memory address (display address) produced on bus 6 by the display address generation circuit 5, display memories 71 and 72 store display information provided by a computer MPU (not shown), and 8-bit display data on buses 81 and 82 are read out of the display memories (A, B) 71 and 72 in accordance with the display address on bus 6. Each address of both display memories 71 and 72 is assigned to a display dot on the liquid crystal display (LCD) panel, and accordingly 8-bit display data 81 and 82 read out of these memories are in a bit-by-bit correspondence.
Indicated by 10 is a parallel-to-serial conversion circuit which converts the 8-bit display data into bit-serial dot data (display data) 111 and 112, and 12 is a lookup table with 2-bit input and 4-bit output in this example which is used for multiple color display and variable color display.
FIG. 2 shows the structure of the lookup table 12. In the figure, indicated by 261 is color information provided by the computer MPU (not shown), 262 is a write address provided by the computer MPU, 121 is a decoder which decodes the write address 262 to produce four kinds of outputs, 122a through 122d are write signals which are the decoded outputs of the decoder 121, and 123a through 123d are 4-bit registers which hold display color information 261 by being strobed by the write signals 122a-122d, respectively. Accordingly, the computer MPU selects one of the registers 123a-123d by issuing the write address 262 of a certain value thereby to set the color information 261 in it.
Indicated by 124a through 124d are 4-bit color information read out of the registers 123a-123d, 125 indicates a selector which selectively conducts one of the four inputs (color information 124a-124d) in response to a 2-bit value of the dot data 111 and 112, and 13 is 4-bit color data selected by the selector 125. Accordingly, based on the values of the dot data 111 and 112 supplied to the lookup table 12, one of color information held in the registers 123a-123d is selected and delivered as color data 13.
Returning to FIG. 1, indicated by 17 is a CRT display unit, which displays the color data 13 from the lookup table 12 as visual information of m dots by n lines. Vertical and horizontal sync signals 18 and 19 are produced from the dot clock 2 by the timing generation circuit 3.
Next, the operation of the display controller arranged as described above will be explained.
Display information stored in locations pointed to by the display address produced on bus 6 which is provided by the display address generation circuit 5 is read out of the display memories 71 and 72. Both information in 8-bit length is fed to the parallel-to-serial conversion circuit 10 as display data 81 and 82. The parallel-to-serial conversion circuit 10 converts the 8-bit display data 81 and 82 into bit-serial data, with each bit representing a dot, and the resulting dot data 111 and 112 are fed to the lookup table 12.
The lookup table 12 stores four sets of color information which have been preset by the computer MPU (not shown) as mentioned above, and it selectively delivers one of four sets of color information as color data to the CRT display unit 17 in response to the value of dot data 111 and 112.
The display address generation circuit 5 generates the display addresses for one frame sequentially, and consequently the CRT display unit 17 is supplied with display data for one frame as color data 13. The CRT display unit 17 displays the dot-wise color data 13 as visual information, and in response to the horizontal sync signal 19, which is produced after m dots have been displayed, it displays data on the next line. This operation is repeated for n lines, and the sequence returns to the top line in response to the vertical sync signal 18.
Through the iteration of the above operations, display information stored in the display memories 71 and 72 is displayed on the CRT display unit 17.
Generally, conventional display apparatus used for such information processing apparatus as work stations and personal computers have their display controller contemplating the reduction of noises created on the display screen during a read access made by the MPU to the lookup table which converts data read out of the display data memory (will be termed "VRAM") into data having the format of the display unit during the period when display data is fed to the screen (will be termed "display period"), as described in Japanese Patent Unexamined Publication No. 62-161194.
Recently, work stations are in a transition of demand from the desktop type using a CRT display unit to the laptop type which is more compact and space-saving by employing a liquid crystal display panel. In order to meet the demand, it is conceivable that the conventional display controller is provided with an additional interface circuit for the liquid crystal panel and is fabricated as a LSI device including peripheral circuitry thereby to attain further compactness. However, the above-mentioned prior art involves difficulties in LSI fabrication, particularly CMOS (Complementary Metal Oxide Semiconductor) LSI fabrication. The problems will be explained with reference to FIG. 3 which is a block diagram of a display controller derived from FIG. 1, with an interface circuit for such a flat display panel as a liquid crystal display panel being added thereto. Portions identical to those of FIG. 1 are referred to by the same symbols and their same arrangement and operation will not be explained.
In the figure, indicated by 15 is a serial-to-parallel conversion circuit which converts the color data 13 read out of the lookup table 12 into data of a certain number of bits for the flat display panel in accordance with the dot clock signal 2, and 161 through 164 are color data provided by the serial-to-parallel conversion circuit 15, i.e., four 4-bit color data for four dots in this example.
Indicated by 171 is a flat display panel having a screen area of m dots by n lines, 20 is a display enable signal indicative of the display period, and 21 is a data shift signal. The flat display panel 171 operates to latch the color data 161-164 sequentially in response to the data shift signal 21 and, after color data of m dots for one line has been latched, displays the data as visual information in response to the horizontal sync signal 19 which is produced for one clock period for every line. This operation is repeated for n lines thereby to display a frame of data.
Assuming that the flat display panel 171 has a resolution of 1,280 dots by 1,024 lines and a frame frequency of 70 Hz, the dot clock signal 2 needs to have a frequency f.sub.DCLK as follows. EQU f.sub.DCLK .gtoreq.1,280.times.1,024.times.70.apprxeq.92 MHz
Accordingly, the timing signal generation circuit 3, parallel-to-serial conversion circuit 10, lookup table 12 and serial-to-parallel conversion circuit 15 need to operate at a speed comparable to 100 MHz, which is too fast for the high-density circuit integration based on the usual CMOS gate arrays or the like due to difficulties in the timing design (if not impossible) and also increased power dissipation.